Note: Follow this link for additional information about each video including
| Week | Date | Topics | Reading | Milestones | |
|---|---|---|---|---|---|
| 1 | Mon. 10 Jan. | Course Overview Introduction Truth Tables Circuit Overview How to build logic gates Use of Binary Hexadecimal and Base Conversions |
Video 0 Sections 1.1 - 1.5 Video 1 (CL1, CL3a) Video 2 (HW1) Video 3 (NR1c,d) Video 4 (NR1) Video 5 (NR3, NR4) Flippy bit A hexadecimal game Tom Lehrer's "New Math" |
Assign First Day Survey Assign In-Class 1: Conversions Assign In-Class 2: Truth Tables and PLAs Assign Homework 1: Relays Assign Homework 2: Introduction to Digital Logic Assign More Conversion Practice |
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| Tue. 11 Jan. | Lab: Tools | Assign Lab 1: Tools | |||
| Wed. 12 Jan. | Truth tables / "Big Hammer" Failure of Big Hammer to Scale Combinatorial Circuits Other Gates Boolean Expressions |
Video 6 Section 2.4 Video 7 Sections 2.1, 2.4, and 2.5 (CL3b) Video 8 Sections 1.5.5 and 1.5.6 Video 9 Section 2.2 (CL3c,d) |
Due First Day Survey Assign In-Class 3: Combinatorial Circuits |
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| Fri. 14 Jan. | Functional Completeness Busses / Bitwise logic operations |
Video 10 (FC1) Section 2.9 |
Assign In-Class 4: Functional Completeness Assign In-Class 5: Busses and Bitwise Operations Discuss HW2 #2-8 Due Lab 1: Tools Due Homework 1: Relays |
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| 2 | Mon. 17 Jan. | No Class | |||
| Tue. 18 Jan. | Lab: Combinatorial Circuits | Assign Lab 2: Introduction to Digital Logic | |||
| Wed. 19 Jan. | Adders Propagation Delay Time of Circuits Circuit Size |
Video 11 Section 5.2 Video 12 Section 1.6 (CL4) Video 13 Section 2.9 Video 14 |
Assign In-Class 6: Adder Assign In-Class 7: Propagation Delay Due Homework 2: Introduction to Digital Logic |
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| Fri. 21 Jan. | |||||
| 3 | Mon. 24 Jan. | Carry Lookahead Adder | Video 15a, Video 15b, Section 5.2 (ADD3cl) |
Due Lab 2: Introduction to Digital Logic | |
| Tue. 25 Jan. | Lab: Unsigned Adder Quiz 1: Conversions and Comb. Circuit Fundamentals |
(NR3, NR4, CL2, CL3) |
Assign Lab 3: Unsigned Adder Assign Project 1: Build an Adder |
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| Wed. 26 Jan. | Carry Lookahead Adder Carry Select Adder "Hybrid" adders / size/time tradeoff Diminishing returns |
Video 15a, Video 15b, Section 5.2 (ADD3cl) Video 16 (ADD3cs) |
Assign In-Class 9: AdvancedAdders | ||
| Fri. 28 Jan. | Signed Integers / Two's Complement Signed Addition |
Video 18 Section 1.4.6 (NR2) Video 19 (ADD4) |
Assign In-Class 8: Two's Complement | ||
| 4 | Mon. 31 Jan. | Mulitplexors 2-to-1 mux is functionally complete Boolean Algebra |
Video 22 (CL5) Section 2.3 (BA1) |
Due Lab 3: Unsigned Adder Assign Homework 3: Boolean Algebra |
|
| Tue. 1 Feb. | Lab: Work on Project 1 Begin Project 2 Quiz 2: |
CL4, ADD3, FC1, [CL1, CL2, CL3] |
Assign Project 1: Build an Adder Assign Project 2: Build a Subtractor and SLT |
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| Wed. 2 Feb. | ALUs Complex Combinatorial Circuits Latches |
Video 22 (CL5) Video 23 Sections 3.1, 3.2, 3.3 (SL1) |
Assign In-Class 10: Circuit with Choices | ||
| Fri. 4 Feb. | Assign In-Class 11: SR-Latch Discuss HW #3 |
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| 5 | Mon. 7 Feb. | Clocks and Clocked Latches | Video 24 (SL2) Clocked D Latch |
Due Project 1: Build an Adder | |
| Tue. 8 Feb. | Quiz 3: Sequential Circuits Lab (Part 1) |
NR2, ADD4, [CL4, ADD3, FC1] | Assign Lab 4: Sequential Circuits | ||
| Wed. 9 Feb. | Flip-Flops Sequential Circuits |
Video 25 Section 3.2.3 (SL2) Video 26 Sections 3.4, 3.5, and 3.6 (SL4, SL6) |
Assign In-Class 12: Flip Flop Timing Assign Homework 4: Sequential Circuits Due Homework 3: Boolean Algebra |
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| Fri. 11 Feb. | Flip-Flops Sequential Circuits |
Video 25 Section 3.2.3 (SL2) Video 26 Sections 3.4, 3.5, and 3.6 (SL4, SL6) |
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| 6 | Mon. 14 Feb. | Finite state Machines Intro to CPU Design, Words, and Registers |
Video 27 Video 28 Sections 7.1 and 7.3.1 |
Discuss HW4 #1-5 | |
| Tue. 15 Feb. | Sequential Circuit Lab (Part 2) Quiz 4: |
CL5, BA1 [NR2, ADD4] | Assign Lab 4: Sequential Circuits | ||
| Wed. 16 Feb. | Machine languge and MIPS R-type Fetch/Execute cycle |
Video 29 Section 6.3 Video 30 Sections 7.1.3 and 7.3.1 |
Assign Project 3: Build an ALU Due Project 2: Build a Subtractor and SLT |
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| Fri. 18 Feb. | Generating and Loading Machine Code | Video 31 | Discuss HW4 #6-8 | ||
| 7 | Mon. 21 Feb. | Assembly Basics Intro to MIPS Assembly |
Video33 Video 34 Sections 6.1, 6.2, 6.3, and 6.4.1 |
Due Lab 4: Sequential Circuits Assign In-Class 13: Assembly Intro Discuss HW4 #9-11 |
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| Tue. 22 Feb. | Assembly Intro Lab Quiz 5: |
Video 35 SL1 [CL5, BA1] |
Assign Lab 5: Introduction to Assembly | ||
| Wed. 23 Feb. | I-Type instructions Design principles |
Video 32 Sections 6.5 and 6.7.1 Video 36 Sections 6.3.2, 7.3.2 and 7.3.3 |
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| Fri. 25 Feb. | Due Homework 4: Sequential Circuits | ||||
| 8 | Mon. 28 Feb. | Jump Branch |
Video 37 Sections 6.3.3, 6.4.2, and 7.3 Video 38 Sections 6.4.2, 6.4.3, and 6.4.4 |
Due Lab 5: Introduction to Assembly | |
| Tue. 1 Mar. | Computer Instruction Types | Assign Lab 6: Computer Instruction Types | |||
| Wed. 2 Mar. | Branch Writing assembly with branches Quiz 6: |
Video 38 Sections 6.4.2, 6.4.3, and 6.4.4 SL2, SL4 [SL1] |
Assign In-Class 14: Branches Assign Homework 5: Branches Due Project 3: Build an ALU |
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| Fri. 4 Mar. | Assign Project 4: Build Single Cycle CPU | ||||
| 9 | Mon. 14 Mar. | Design principles Load and Store |
Sections 6.3.2, 7.3.2 and 7.3.3 Section 6.4.5 |
Due Lab 6: Computer Instruction Types | |
| Tue. 15 Mar. | Loops and Memory | Assign Lab 7: Loops and Memory | |||
| Wed. 16 Mar. | using .data in Assembly Load Store implementation Writing assembly with loops and memory |
Section 6.4.5 |
Assign Homework 6: Single Cycle CPU Assign In-Class 15: Loops |
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| Fri. 18 Mar. | Quiz 7: | SL6, AL2 [SL2, SL4] | |||
| 10 | Mon. 21 Mar. | Control Wires | Single Cycle Control Wires | Due Homework 5: Branches Assign In-Class 16: Control Wires |
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| Tue. 22 Mar. | Loops and Memory (part 2) (Also time to work on Project 4) |
Assign Lab 7: Loops and Memory | |||
| Wed. 23 Mar. | Function calls Clobbered Registers Using "s" registers Heap and Stack |
Video 39 Section 6.4.6 Video 40 Video 41 Section 6.4.6 |
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| Fri. 25 Mar. | Quiz 8: | AL3, AL4, AL5 [SL6, AL2] | |||
| 11 | Mon. 28 Mar. | Single Cycle Performance CISC vs. RISC |
Sections 7.2 and 7.3.4 | Due Lab 7: Loops and Memory | |
| Tue. 29 Mar. | Recursion | Assign Lab 8: Recursion | |||
| Wed. 30 Mar. | RAM SRAM Implementation DRAM Implementation SRAM vs. DRAM Memory layout |
Section 8.1 Section 8.3 |
Due Homework 6: Single Cycle CPU | ||
| Fri. 1 Apr. | Memory Heirarchy Motivation for caches Direct Mapped Cache Cache Block Size |
Video 45 Section 8.1 Memory Heirarchy Video 46 Section 8.3 Video 47 |
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| 12 | Mon. 4 Apr. | Set Associative caches Cache replacement policy LRU and Pseudo-LRU |
Video 49 Section 8.3 Video 50 Video 51 |
Due Lab 8: Recursion Due Project 4 (Phase 1) |
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| Tue. 5 Apr. | Cache Lab (part 1) | Assign Lab 9: Cache (part 1) | |||
| Wed. 6 Apr. | LRU and Pseudo-LRU Split/Unified cache Write Through / Write Back cache |
Video 51 |
Assign Homework 7: Cache | ||
| Fri. 8 Apr. | Quiz 9: | SS3, SS4, SS5, [AL3, AL4, AL5] | |||
| 13 | Mon. 11 Apr. | Pipelining Data Hazards |
Intro to Pipelining Step through pipelined program |
Due Lab 9: Cache (part 1) Due Project 4: Build Single Cycle CPU |
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| Tue. 12 Apr. | Cache Lab (part 2) | Assign Lab 10: Cache (part 2) | |||
| Wed. 13 Apr. | Pipelining Data Hazards Control Hazards Pipeline speedup / Limitations |
Intro to Pipelining Step through pipelined program |
Due Homework 7: Cache Assign Homework 8: Pipeline Implementation Assign Homework 9: Pipeline Performance |
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| Fri. 15 Apr. | Quiz 10: | M2, M3, M4, [SS3, SS4, SS5] | Due Lab 10: Cache (part 2) | ||
| 14 | Mon. 18 Apr. | More Single Cycle Performance Superscalar |
Sections 7.2 and 7.3.4 | ||
| Tue. 19 Apr. | Pipelining | Assign Lab 11: Pipeline | |||
| Wed. 20 Apr. | Interrupts Karnaugh Maps |
K-Map Introduction 4-variable K-map |
Due Homework 8: Pipeline Implementation Due Homework 9: Pipeline Performance Due Lab 10: Cache (part 2) |
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| Fri. 22 Apr. | Quiz 11: | P1, P2 [M2, M3, M4] | Due Lab 11: Pipeline | ||
| 15 | Mon. 25 Apr. | Final Exam: 2:00 p.m. | (For Section 01 meeting MWF at 3:00) | ||
| Tue. 26 Apr. | |||||
| Wed. 27 Apr. | Final Exam: 8:00 a.m. | (For Section 03 meeting MWF at 9:00) | |||
| Fri. 29 Apr. |
| Due | Name | Details |
|---|---|---|
| Wed. 12 Jan. | First Day Survey | |
| Fri. 14 Jan. | Homework 1: Relays | |
| Wed. 19 Jan. | Homework 2: Introduction to Digital Logic | Problems 9 - 12 only |
| Mon. 7 Feb. | Project 1: Build an Adder | |
| Wed. 9 Feb. | Homework 3: Boolean Algebra | Problems 8h, 8i, and 8j only |
| Wed. 16 Feb. | Project 2: Build a Subtractor and SLT | |
| Fri. 25 Feb. | Homework 4: Sequential Circuits | Problems 12, 13, and 14 only |
| Wed. 2 Mar. | Project 3: Build an ALU | |
| Mon. 21 Mar. | Homework 5: Branches | |
| Wed. 30 Mar. | Homework 6: Single Cycle CPU | Please work in pairs. |
| Mon. 4 Apr. | Project 4 (Phase 1) | |
| Mon. 11 Apr. | Project 4: Build Single Cycle CPU | Please work in pairs |
| Wed. 13 Apr. | Homework 7: Cache | Problems 1 - 6 only. |
| Wed. 20 Apr. | Homework 9: Pipeline Performance | Not due for credit |
| Wed. 20 Apr. | Homework 8: Pipeline Implementation |
| Date | Name | Details |
|---|---|---|
| Tue. 11 Jan. | Lab 1: Tools | Individual assignment |
| Tue. 18 Jan. | Lab 2: Introduction to Digital Logic | |
| Tue. 25 Jan. | Lab 3: Unsigned Adder | |
| Tue. 15 Feb. | Lab 4: Sequential Circuits | |
| Tue. 22 Feb. | Lab 5: Introduction to Assembly | |
| Tue. 1 Mar. | Lab 6: Computer Instruction Types | |
| Tue. 22 Mar. | Lab 7: Loops and Memory | |
| Tue. 29 Mar. | Lab 8: Recursion | |
| Tue. 5 Apr. | Lab 9: Cache (part 1) | |
| Tue. 12 Apr. | Lab 10: Cache (part 2) | |
| Tue. 19 Apr. | Lab 11: Pipeline |
Updated Sunday, 24 April 2022, 7:09 PM