CIS 351 |
Project 2: Build a Subtractor and Comparator |
Winter 2022 |
Extend your signed adder from the previous project to build
Build a circuit that can do both addition and subtraction. Specifically, surround your adder with additional gates so that it performs both addition and subtraction. This circuit should contain one adder only. Be sure to ask for clarification if you don't understand this requirement.
Place your Adder/Subtractor in SignedAddSubtract_16bit.jls
.
Do not change the names of the input or output pins.
The Op
input specifies whether to perform addition or subtraction.
(1
means subtract, 0
means add).
The CarryOut
and Overflow
outputs should simply be the carry out and overflow from your
adder. Unsigned subtraction cannot overflow. Unsigned subtraction that generates a negative result is not considered
"overflow".
You may use SampleSigned16BitAddSubtractTest.java
as a
basis for your own tests. Warning! This test class is incomplete. Don't assume that a circuit that
passes this sample test will pass all of my tests.
Build a circuit that can compare two integers. It must support both signed and unsigned comparisons.
Use your adder/subtractor as a starting point and leverage the fact that
A < B
, then A - B < 0
, andA ≥ B
, then A - B ≥ 0
.
Be aware, however, that this algorithm works only as long as A - B
doesn't overflow. You'll need to
think about the conditions under which A - B
might overflow and use alternate techniques for comparing
A
and B
in this case. (Hint: Don't try to detect and react to overflow. That doesn't
tend to work well. Instead, think about the conditions under which you might have an overflow.)
Place your comparison circuit in Slt_16bit.jls
.
Do not change the names of the input or output pins.
You may use SampleSlt16BitTest.java
as a
basis for your own tests. Warning! This test script is incomplete. Don't assume that a circuit that
passes this sample test will pass all of my tests.
JLS
and DLUnit
. Commit and push your circuits often.
You are expected to revise your circuits until both (1) the automated tests pass, and (2) your circuit design and layout have earned a score of "E" or "M". Project "Late Days" will accumulate until both requirements have been satisfied. Remember: There are two separate sets of tests to run.
You can accumulate up to -1 Late Days if you project meets all requirements before the deadline. (Negative Late Days can be used to offset any Late Days acquired on other projects or labs.)
To submit your project:
jls
files that includes the names of everybody on the team.
[Grade Me]
to the commit message.Updated Tuesday, 8 February 2022, 3:21 PM