Note: Follow this link for additional information about each video including
| Week | Date | Topics | Reading | Milestones | |
|---|---|---|---|---|---|
| 1 | Mon. 30 Aug. | Course Overview Introduction Truth Tables Circuit Overview How to build logic gates Use of Binary Hexadecimal and Base Conversions |
Video 0 Sections 1.1 - 1.5 Video 1 Video 2 Video 3 Video 4 Video 5 Flippy bit A hexadecimal game Tom Lehrer's "New Math" |
Assign First Day Survey Assign In-Class 1: Conversions Assign Homework 1: Introduction to Digital Logic Assign More Conversion Practice |
|
| Tue. 31 Aug. | Lab: Conversions | Assign Lab 1: Number Conversions | |||
| Wed. 1 Sep. | Truth tables / "Big Hammer" Failure of Big Hammer to Scale Combinatorial Circuits Other Gates |
Video 6 Section 2.4 Video 7 Sections 2.1, 2.4, and 2.5 Video 8 Sections 1.5.5 and 1.5.6 |
Assign In-Class 2: Truth Tables and PLAs Assign In-Class 3: Combinatorial Circuits Due First Day Survey |
||
| Fri. 3 Sep. | |||||
| 2 | Mon. 6 Sep. | No Class | |||
| Tue. 7 Sep. | Lab: Combinatorial Circuits | Assign Lab 2: Introduction to Digital Logic | |||
| Wed. 8 Sep. | Boolean Expressions Functional Completeness Busses / Bitwise logic operations |
Video 9 Section 2.2 Video 10 Section 2.9 |
Assign In-Class 3: Combinatorial Circuits (cntd.) Due Lab 1: Number Conversions |
||
| Fri. 10 Sep. | |||||
| 3 | Mon. 13 Sep. | Adders Propagation Delay Time of Circuits Circuit Size |
Video 11 Section 5.2 Video 12 Section 1.6 Video 13 Section 2.9 Video 14 |
Due Lab 2: Introduction to Digital Logic Due Homework 1: Introduction to Digital Logic Assign In-Class 4: Propagation Delay Assign In-Class 5: Adder |
|
| Tue. 14 Sep. | Lab: Unsigned Adder Quiz 1: Conversions and Comb. Circuit Fundamentals |
NR1, NR3, NR4, CL1, CL2, CL3 |
Assign Lab 3: Unsigned Adder Assign Project 1: Build an Adder |
||
| Wed. 15 Sep. | Carry Lookahead Adder Carry Select Adder "Hybrid" adders / size/time tradeoff Diminishing returns |
Video 15a]], [[https://youtu.be/Bf6plMrj7-Y Video 15b, Section 5.2 Video 16 |
Assign In-Class 7: AdvancedAdders | ||
| Fri. 17 Sep. | |||||
| 4 | Mon. 20 Sep. | Signed Integers / Two's Complement Signed Addition |
Video 18 Section 1.4.6 Video 19 |
Due Lab 3: Unsigned Adder Assign In-Class 6: Two's Complement |
|
| Tue. 21 Sep. | Lab: Work on Project 1 Begin Project 2 Quiz 2: |
CL4, ADD1, ADD2, FC1 |
Assign Project 1: Build an Adder Assign Project 2: Build a Subtractor and SLT |
||
| Wed. 22 Sep. | Mulitplexors 2-to-1 mux is functionally complete Boolean Algebra |
Video 22 Section 2.3 |
Assign Homework 2: Boolean Algebra | ||
| Fri. 24 Sep. | |||||
| 5 | Mon. 27 Sep. | ALUs Complex Combinatorial Circuits Latches |
Video 22 Video 23 Sections 3.1, 3.2, 3.3 |
Due Project 1: Build an Adder Assign In-Class 8: Circuit with Choices Assign In-Class 9: SR-Latch |
|
| Tue. 28 Sep. | Quiz 3: Begin Project 2 |
NR2, ADD3, ADD4, ADD5 | Assign Project 2: Build a Subtractor and SLT | ||
| Wed. 29 Sep. | Clocks and Clocked Latches | Video 24 | Assign In-Class 10: Flip Flop Timing Assign Homework 3: Sequential Circuits |
||
| Fri. 1 Oct. | |||||
| 6 | Mon. 4 Oct. | Flip-Flops Sequential Circuits |
Video 25 Section 3.2.3 Video 26 Sections 3.4, 3.5, and 3.6 |
Due Homework 2: Boolean Algebra | |
| Tue. 5 Oct. | Sequential Circuit Lab | Assign Lab 4: Sequential Circuits | |||
| Wed. 6 Oct. | Finite state Machines | Video 27 | Assign Project 3: Build an ALU | ||
| Fri. 8 Oct. | |||||
| 7 | Mon. 11 Oct. | Intro to CPU Design, Words, and Registers Machine languge and MIPS R-type Fetch/Execute cycle Generating and Loading Machine Code Assembly Basics Intro to MIPS Assembly |
Video 28 Sections 7.1 and 7.3.1 Video 29 Section 6.3 Video 30 Sections 7.1.3 and 7.3.1 Video 31 Video33 Video 34 Sections 6.1, 6.2, 6.3, and 6.4.1 |
Due Project 2: Build a Subtractor and SLT Due Lab 4: Sequential Circuits Assign In-Class 11: Assembly Intro |
|
| Tue. 12 Oct. | Assembly Intro Lab Quiz 4: |
Video 35 CL5, BA1 |
Assign Lab 5: Introduction to Assembly | ||
| Wed. 13 Oct. | I-Type instructions Design principles |
Video 32 Sections 6.5 and 6.7.1 Video 36 Sections 6.3.2, 7.3.2 and 7.3.3 |
|||
| Fri. 15 Oct. | Due Homework 3: Sequential Circuits | ||||
| 8 | Mon. 18 Oct. | Jump Branch |
Video 37 Sections 6.3.3, 6.4.2, and 7.3 Video 38 Sections 6.4.2, 6.4.3, and 6.4.4 |
Due Lab 5: Introduction to Assembly | |
| Tue. 19 Oct. | Computer Instruction Types | Assign Lab 6: Computer Instruction Types | |||
| Wed. 20 Oct. | Branch Writing assembly with branches Quiz 5: |
Video 38 Sections 6.4.2, 6.4.3, and 6.4.4 SL1 |
Assign In-Class 12: Branches Assign Homework 4: Branches Due Project 3: Build an ALU |
||
| Fri. 22 Oct. | |||||
| 9 | Mon. 25 Oct. | Fall Break | Due Lab 6: Computer Instruction Types | ||
| Tue. 26 Oct. | Fall Break | ||||
| Wed. 27 Oct. | Design principles Load and Store using .data in Assembly Load Store implementation Writing assembly with loops and memory |
Sections 6.3.2, 7.3.2 and 7.3.3 Section 6.4.5 Section 6.4.5 |
Assign Homework 5: Single Cycle CPU Assign In-Class 13: Loops |
||
| Fri. 29 Oct. | |||||
| 10 | Mon. 1 Nov. | Control Wires Quiz 6: |
| Single Cycle Control Wires SL2, SL4 |
Due Homework 4: Branches Assign Project 4: Build Single Cycle CPU Assign In-Class 14: Control Wires |
|
| Tue. 2 Nov. | Loops and Memory | Assign Lab 7: Loops and Memory | |||
| Wed. 3 Nov. | Control Wires Quiz 6b: |
Make-up only (CL5, SL1) |
|||
| Fri. 5 Nov. | |||||
| 11 | Mon. 8 Nov. | Single Cycle Performance Karnaugh Maps Function calls Clobbered Registers Using "s" registers Heap and Stack |
Sections 7.2 and 7.3.4 K-Map Introduction 4-variable K-map Video 39 Section 6.4.6 Video 40 Video 41 Section 6.4.6 |
Due Lab 7: Loops and Memory | |
| Tue. 9 Nov. | Recursion Quiz 7: |
SL6, AL1 |
Assign Lab 8: Recursion | ||
| Wed. 10 Nov. | RAM SRAM Implementation DRAM Implementation SRAM vs. DRAM Memory layout |
Section 8.1 Section 8.3 |
Due Homework 5: Single Cycle CPU | ||
| Fri. 12 Nov. | |||||
| 12 | Mon. 15 Nov. | Memory Heirarchy Motivation for caches Direct Mapped Cache Cache Block Size |
Video 45 Section 8.1 Memory Heirarchy Video 46 Section 8.3 Video 47 |
Due Lab 8: Recursion Due Project 4 (Phase 1) |
|
| Tue. 16 Nov. | Cache Lab (part 1) | Assign Lab 9: Cache (part 1) | |||
| Wed. 17 Nov. | Set Associative caches Cache replacement policy LRU and Pseudo-LRU Split/Unified cache Write Through / Write Back cache Quiz 8: |
Video 49 Section 8.3 Video 50 Video 51 AL3, SL1, AL1 |
Assign Homework 6: Cache | ||
| Fri. 19 Nov. | |||||
| 13 | Mon. 22 Nov. | Karnaugh Maps Set Associative caches Cache replacement policy LRU and Pseudo-LRU Split/Unified cache Write Through / Write Back cache Pipelining Data Hazards |
K-Map Introduction 4-variable K-map Video 49 Section 8.3 Video 50 Video 51 Intro to Pipelining Step through pipelined program |
Due Lab 9: Cache (part 1) | |
| Tue. 23 Nov. | Cache Lab (part 2) Quiz 9: |
AL2, SL2, SL6 |
Assign Lab 10: Cache (part 2) | ||
| Wed. 24 Nov. | No Class | ||||
| Fri. 26 Nov. | No Class | ||||
| 14 | Mon. 29 Nov. | Pipelining Data Hazards Control Hazards Pipeline speedup / Limitations |
Intro to Pipelining Step through pipelined program |
Due Homework 6: Cache Assign Homework 7: Pipeline Implementation Assign Homework 8: Pipeline Performance |
|
| Tue. 30 Nov. | Pipelining | Assign Lab 11: Pipeline Due Project 4: Build Single Cycle CPU |
|||
| Wed. 1 Dec. | Superscalar Quiz 10: |
SS3, SS5, (SL4, AL2, AL3, SL6) | Due Lab 10: Cache (part 2) | ||
| Fri. 3 Dec. | |||||
| 15 | Mon. 6 Dec. | Single Cycle Performance SRAM vs. DRAM |
Sections 7.2 and 7.3.4 | Due Lab 11: Pipeline | |
| Tue. 7 Dec. | Quiz 11: | SS4, M2, M3, M4, P1, (SS3, SS5) (Other re-takes as requested) |
|||
| Wed. 8 Dec. | Interrupts CISC cs. RISC |
Due Homework 7: Pipeline Implementation Due Homework 8: Pipeline Performance |
|||
| Fri. 10 Dec. | |||||
| 16 | Mon. 13 Dec. | Final Exam: 8:00 a.m. | (For Section 01 meeting MWF at 8:00) | ||
| Tue. 14 Dec. | |||||
| Wed. 15 Dec. | Final Exam: 4:00 p.m. | (For Section 02 meeting MW at 4:00) | |||
| Fri. 17 Dec. |
| Due | Name | Details |
|---|---|---|
| Wed. 1 Sep. | First Day Survey | |
| Mon. 13 Sep. | Homework 1: Introduction to Digital Logic | |
| Mon. 27 Sep. | Project 1: Build an Adder | |
| Mon. 4 Oct. | Homework 2: Boolean Algebra | |
| Mon. 11 Oct. | Project 2: Build a Subtractor and SLT | |
| Fri. 15 Oct. | Homework 3: Sequential Circuits | |
| Wed. 20 Oct. | Project 3: Build an ALU | |
| Mon. 1 Nov. | Homework 4: Branches | |
| Wed. 10 Nov. | Homework 5: Single Cycle CPU | Please work in pairs. |
| Mon. 15 Nov. | Project 4 (Phase 1) | |
| Mon. 29 Nov. | Homework 6: Cache | Problems 1 - 6 only. |
| Tue. 30 Nov. | Project 4: Build Single Cycle CPU | Please work in pairs |
| Wed. 8 Dec. | Homework 7: Pipeline Implementation | |
| Wed. 8 Dec. | Homework 8: Pipeline Performance | Not due for credit |
| Date | Name | Details |
|---|---|---|
| Tue. 31 Aug. | Lab 1: Number Conversions | Individual assignment |
| Tue. 7 Sep. | Lab 2: Introduction to Digital Logic | |
| Tue. 14 Sep. | Lab 3: Unsigned Adder | |
| Tue. 5 Oct. | Lab 4: Sequential Circuits | |
| Tue. 12 Oct. | Lab 5: Introduction to Assembly | |
| Tue. 19 Oct. | Lab 6: Computer Instruction Types | |
| Tue. 2 Nov. | Lab 7: Loops and Memory | |
| Tue. 9 Nov. | Lab 8: Recursion | |
| Tue. 16 Nov. | Lab 9: Cache (part 1) | |
| Tue. 23 Nov. | Lab 10: Cache (part 2) | |
| Tue. 30 Nov. | Lab 11: Pipeline |
Updated Friday, 10 December 2021, 2:45 PM