| Week | Date | Topics | Notes | Reading | Milestones |
|---|---|---|---|---|---|
| 1 | Mon. 31 Aug. | Introduction Truth Tables Circuit Overview How to build logic gates Use of Binary Hexadecimal and Base Conversions |
Sections 1.1 - 1.5 Video 1 Video 2 Video 3 Video 4 Video 5 |
Assign First Day Survey Assign Homework 1: Introduction to Digital Logic Assign In-Class 1: Conversions Assign In-Class 2: Truth Tables and PLAs |
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| Tue. 1 Sep. | Lab: Tools | Assign Lab 1: Tools Due First Day Survey |
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| Wed. 2 Sep. | Course Overview / Logistics | Video 0 | |||
| Fri. 4 Sep. | Transistors Building logic gates with transistors Power Consumption |
Building Transistors Section 1.7 Section 1.8 |
Due Lab 1: Tools | ||
| 2 | Mon. 7 Sep. | Labor Day | |||
| Tue. 8 Sep. | Lab: Conversions | Assign Lab 2: Number Conversions | |||
| Wed. 9 Sep. | Failure of Big Hammer to Scale Combinatorial Circuits Other Gates Boolean Expressions Functional Completeness |
Video 6 Section 2.4 Video 7 Sections 2.1, 2.4, and 2.5 Video 8 Sections 1.5.5 and 1.5.6 Video 9 Section 2.2 Video 10 |
Assign In-Class 3: Combinatorial Circuits | ||
| 3 | Mon. 14 Sep. | Adders Propagation Delay Time of Circuits Circuit Size Carry Lookahead Adder Carry Select Adder Test 1: Conversions |
Video 11 Section 5.2 Video 12 Section 1.6 Video 13 Section 2.9 Video 14 Video 15 Section 5.2 Video 16 |
Due Lab 2: Number Conversions Assign In-Class 4: Propagation Delay |
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| Tue. 15 Sep. | Lab: Unsigned Adder | Assign Lab 3: Unsigned Adder Assign Project 1: Build an Adder |
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| Wed. 16 Sep. | Ripple Carry Adder in-class exercise | Assign Introduction to JLS Due Homework 1: Introduction to Digital Logic Assign Project 1: Build an Adder |
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| 4 | Mon. 21 Sep. | Carry Lookahead Adder^ Carry Select Adder^ Signed Integers / Twos Complement Signed Addition Mulitiplexors Boolean Algebra ALUs Test 2: Combinatorial Circuits |
Video 15 Section 5.2 Video 16 Video 18 Section 1.4.6 Video 19 Section 2.3 |
Due Lab 3: Unsigned Adder Assign Homework 2: Boolean Algebra |
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| Tue. 22 Sep. | Combinatorial Circuits Lab | Assign Lab 4: Introduction to Digital Logic | |||
| Wed. 23 Sep. | Assign Project 2: Build a Subtractor and SLT Assign Project 3: Build an ALU |
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| 5 | Mon. 28 Sep. | Signed Integers / Twos Complement^ Signed Addition^ Mulitiplexors^ Boolean Algebra^ ALUs |
Video 18 Section 1.4.6 Video 19 Video 22 Section 2.3 |
Due Lab 4: Introduction to Digital Logic Assign in-Class 5: Circuit with Choices |
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| Tue. 29 Sep. | Subtraction and Comparison | Assign Lab 5: Subtraction and Comparison | |||
| Wed. 30 Sep. | Due Project 1: Build an Adder | ||||
| Fri. 2 Oct. | |||||
| 6 | Mon. 5 Oct. | Latches Clocks and Clocked Latches Flip-Flops Sequential Circuits Finite state Machines |
Video 23 Sections 3.1, 3.2, 3.3 Video 24 Video 25 Section 3.2.3 Video 26 Sections 3.4, 3.5, and 3.6 Video 27 |
Assign In-Class 6: Flip Flop Timing Assign Homework 3: Sequential Circuits Due Homework 2: Boolean Algebra |
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| Tue. 6 Oct. | ALUs | Assign Lab 6: ALUs | |||
| Wed. 7 Oct. | Flip Flops and Sequential Circuits | Due Project 2: Build a Subtractor and SLT | |||
| Fri. 9 Oct. | Finite State Machines | ||||
| 7 | Mon. 12 Oct. | Intro to CPU Design, Words, and Register Files Intro to Assembly Machine languge and MIPS R-type Fetch/Execute cycle Generating and Loading Machine Code I-Type instructions Design principles Test 3: |
Video 28 Sections 7.1 and 7.3.1 Sections 6.1, 6.2, 6.3, and 6.4.1 Video 29 Section 6.3 Video 30 Sections 7.1.3 and 7.3.1 Video 31 Sections 6.5 and 6.7.1 Sections 6.3.2, 7.3.2 and 7.3.3 |
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| Tue. 13 Oct. | Assembly Intro Lab Sequential Circuits Lab |
Assign Lab 7: Introduction to Assembly Assign Lab 7: Sequential Circuits |
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| Wed. 14 Oct. | |||||
| Fri. 16 Oct. | Due Homework 3: Sequential Circuits Due Project 3: Build an ALU |
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| 8 | Mon. 19 Oct. | "Second Chance" Test ^ Machine Language and MIPS R-type ^ Fectch/Execute cycle ^ Generating and Loading Machine Code ^ I-Type instructions ^ Design principles Branch and Jump |
Video 29 Section 6.3 Video 30 Sections 7.1.3 and 7.3.1 Video 31 (in person only) Sections 6.5 and 6.7.1 Sections 6.3.2, 7.3.2 and 7.3.3 Sections 6.3.3, 6.4.2, 6.4.3 |
Due Lab 7: Introduction to Assembly Due Lab 7: Sequential Circuits |
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| Tue. 20 Oct. | Assembly Branches Lab | Assign Lab 8: Assembly Branches | |||
| Wed. 21 Oct. | |||||
| Fri. 23 Oct. | |||||
| 9 | Mon. 26 Oct. | Jump Branch Load and Store using .data in Assembly Load Store implementation |
Video 34 Sections 6.3.3, 6.4.2, and 7.3 Video 35 Sections 6.4.2, 6.4.3, and 6.4.4 (in person only) Section 6.4.5 |
Due Lab 8: Assembly Branches | |
| Tue. 27 Oct. | Assign Lab 9: Computer Instruction Types | ||||
| Wed. 28 Oct. | Assign Homework 4: Single Cycle CPU Assign Sequential Circuits Review |
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| Fri. 30 Oct. | |||||
| 10 | Mon. 2 Nov. | Function calls Clobbered Registers Using "s" registers Heap and Stack System calls Single Cycle Performance Interrupts Test 4: Sequential Circuits |
Video 39 Section 6.4.6 Video 40 Video 41 Section 6.4.6 Sections 7.2 and 7.3.4 Section 6.7.2 |
Due Lab 9: Computer Instruction Types Due Sequential Circuits Review Assign Assembly Review |
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| Tue. 3 Nov. | Loops and Memory | Assign Lab 10: Loops and Memory | |||
| Wed. 4 Nov. | Assign In-Class 7: Control Wires | ||||
| Fri. 6 Nov. | Due Homework 4: Single Cycle CPU | ||||
| 10 | Mon. 9 Nov. | RAM SRAM Implementation DRAM Implementation SRAM vs. DRAM Memory layout Memory Heirarchy (Motivation for caches) Direct Mapped Cache Cache Block Size Test 5: Assembly Branches |
Section 8.1 Section 8.3 Video 45 Section 8.1 Video 46 Section 8.3 Video 47 |
Due Assembly Review Assign Homework 5: Cache |
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| Tue. 10 Nov. | CPU Project | Assign Lab 11: Build Single Cycle CPU | |||
| Wed. 11 Nov. | Due Homework 4: Single Cycle CPU Due Lab 10: Loops and Memory |
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| Fri. 13 Nov. | |||||
| 11 | Mon. 16 Nov. | Set Associative caches Cache replacement policy LRU and Pseudo-LRU Split/Unified cache Test 6: Memory and Loops |
Video 49 Section 8.3 Video 50 Video 51 |
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| Tue. 17 Nov. | Cache 1 and 2 | Assign Lab 12: Cache (part 1) Assign Lab 12: Cache (part 2) |
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| Wed. 18 Nov. | |||||
| Fri. 20 Nov. | Due Project 4 (Phase 1) | ||||
| 12 | Mon. 23 Nov. | Test 7: Final Exam (part 1) | |||
| Tue. 24 Nov. | Cache 2 (continued) | Due Lab 12: Cache (part 1) | |||
| Wed. 25 Nov. | No class | Due Homework 5: Cache | |||
| Fri. 27 Nov. | No class | Assign Homework 6: Pipeline Implementation | |||
| 13 | Mon. 30 Nov. | Pipelining Data Hazards Control Hazards Karnaugh Maps |
Intro to Pipelining K-Map Introduction 4-variable K-map |
Due Lab 12: Cache (part 2) | |
| Tue. 1 Dec. | Pipeline Lab | Assign Lab 13: Pipeline | |||
| Wed. 2 Dec. | Pipeline speedup / Limitations Split / Unified cache |
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| Fri. 4 Dec. | |||||
| 14 | Mon. 7 Dec. | More Pipelining MIPS Calling Conventions |
Video 39 Section 6.4.6 Video 40 Video 41 |
Due Lab 11: Build Single Cycle CPU Due Lab 13: Pipeline Assign Homework 7: Pipeline Performance |
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| Tue. 8 Dec. | Recursion Lab | Assign Lab 14: Recursion | |||
| Wed. 9 Dec. | |||||
| Fri. 11 Dec. | |||||
| 15 | Mon. 14 Dec. | Final Exam | Due Homework 6: Pipeline Implementation Due Homework 7: Pipeline Performance Due Practice Final |
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| Tue. 15 Dec. | Due Lab 14: Recursion | ||||
| Wed. 16 Dec. | |||||
| Fri. 18 Dec. |
| Due | Name | Details |
|---|---|---|
| Tue. 1 Sep. | First Day Survey | |
| Wed. 16 Sep. | Homework 1: Introduction to Digital Logic | Due at 5:15 p.m. Please submit hard-copy |
| Wed. 30 Sep. | Project 1: Build an Adder | |
| Mon. 5 Oct. | Homework 2: Boolean Algebra | |
| Wed. 7 Oct. | Project 2: Build a Subtractor and SLT | |
| Fri. 16 Oct. | Homework 3: Sequential Circuits | |
| Fri. 16 Oct. | Project 3: Build an ALU | |
| Mon. 2 Nov. | Sequential Circuits Review | Not due for credit |
| Mon. 9 Nov. | Assembly Review | Not due for credit |
| Wed. 11 Nov. | Homework 4: Single Cycle CPU | Please work in pairs. |
| Fri. 20 Nov. | Project 4 (Phase 1) | |
| Wed. 25 Nov. | Homework 5: Cache | Problems 1 - 6 only. |
| Mon. 14 Dec. | Homework 7: Pipeline Performance | Not due for credit |
| Mon. 14 Dec. | Homework 6: Pipeline Implementation | |
| Mon. 14 Dec. | Practice Final | Not due for credit |
| Date | Name | Details |
|---|---|---|
| Tue. 1 Sep. | Lab 1: Tools | |
| Tue. 8 Sep. | Lab 2: Number Conversions | |
| Tue. 15 Sep. | Lab 3: Unsigned Adder | |
| Tue. 22 Sep. | Lab 4: Introduction to Digital Logic | |
| Tue. 29 Sep. | Lab 5: Subtraction and Comparison | Get started on Project 2 |
| Tue. 6 Oct. | Lab 6: ALUs | Get started on Project 3 |
| Tue. 13 Oct. | Lab 7: Sequential Circuits | |
| Tue. 13 Oct. | Lab 7: Introduction to Assembly | |
| Tue. 20 Oct. | Lab 8: Assembly Branches | |
| Tue. 27 Oct. | Lab 9: Computer Instruction Types | |
| Tue. 3 Nov. | Lab 10: Loops and Memory | |
| Tue. 10 Nov. | Lab 11: Build Single Cycle CPU | Please work in pairs |
| Tue. 17 Nov. | Lab 12: Cache (part 1) | |
| Tue. 17 Nov. | Lab 12: Cache (part 2) | |
| Tue. 1 Dec. | Lab 13: Pipeline | |
| Tue. 8 Dec. | Lab 14: Recursion |
Updated Wednesday, 2 December 2020, 5:48 PM