For this project, you will use JLS to implement a signed adder.

You are strongly encouraged to work in teams of two.

Begin by following this GitHub Classroom link to create the repository for this project. You may want to copy your unsigned adder from the lab into this new repo.

Task

Implement a 16-bit signed adder using any algorithm you wish, provided the circuit has a reasonable running time and size. Faster adders will receive more points. (See Grading section below.) Your adder must report overflow conditions when they occur (with respect to signed inputs). Notice that this circuit must have an input named CarryIn. You will use this input for future projects.

The starter code contains a file named SignedAdder_16bit.jls. You must place your solution in this file. Do not change the names of any of the inputs or outputs. (If you change the filename or the names of any inputs/outputs, the automated tests will not work.))

CarryOut is the carry out from the last full adder. It is also, in effect, the overflow indicator for unsigned inputs. Overflow is the overflow indicator for signed inputs. Remember, CarryOut and Overflow will not necessarily have the same value.

You may use SampleSigned16BitAdderTest.java as a basis for your own tests. Warning! This test file is incomplete. Don't assume that a circuit that passes this sample test will pass all of my tests.

Rules

1. You are strongly encouraged to work in groups of two. You may work alone only with permission of the instructor.
2. You may use your unsigned adder from the lab.
3. The simulator comes with a built-in adder. You may not use the built-in adder.
4. To build the required circuits, you will probably find it useful to design and build several subcircuits. These subcircuits may have any interface you choose; however, you are responsible for testing them.
5. You must write all of your own chips. In other words, you may not share "internal" chips with your classmates, or download them off the Internet.
6. Be sure to test your components thoroughly. Just because it passes the test included here doesn't mean it will pass my test.

Hints and shortcuts

• Remember, JLS inserts the code for sub-circuits directly into the circuits into which they are imported. Thus, changes to sub-circuits are not seen by the circuits that contain them. If you discover a bug in a sub-circuit, you must delete and re-import that sub-circuit into the parent. (Again, test your subcircuits thoroughly before importing them!)
• Remember that no software is perfect. This includes JLS and DLUnit. Commit and push your code often. That way, if JLS does crash you won't lose too much work. Also, please e-mail me with any bugs you find or feature requests you have. If JLS crashes, please e-mail me the JLSerror file.

Grading

This assignment will be scored out of 100 points.

^*For 5 points, correctly specify the exact number of gates used by your adder (the total number of gates, including all sub-circuits) and the time required by your adder (i.e., the sum of all the gate delays along the critical path).

Penalties

• You will loose points if your circuits are not neat and well-documented.

Deliverables

To submit your project:

1. Add a text box to your jls files that includes the names of all team members.
2. Your adder should also include a label indicating time and gate count. The time should be the maximum simulation needed for any addition. (I'm looking for an actual number, not a big-O expression.)
3. When your adder passes the automated tests, and contains the time/size information, push your project with [Grade Me] in the commit message.

Updated Sunday, 20 September 2020, 5:47 PM