| Week | Date | Topics | Reading | Milestones |
|---|---|---|---|---|
| 1 | Mon. 26 Aug. | Introduction What is Computer Architecture Transistors Key factors in performance trends Current challenges in improvign performance RISC vs. CISC Power and Energy |
History and Benchmarking H&P Sections 1.1, 1.3, 1.4, and 1.5 Veritasium transistor videos Overview of RISC vs. CISC |
Assign First Day Survey |
| 2 | Mon. 9 Sep. | Performance Overview Carefully describing performance ISA Design |
H&P Sections 1.7 and 1.9 Architecture, Language, and Compiler History |
Due First Day Survey |
| 3 | Mon. 16 Sep. | Addressing modes Load/Store vs. Register Memory Performance of Single Cycle CPU Multi-cycle CPU Intel machine language Quantum Computing, Part 1 |
H&P Appendix A Harris and Harris Section 7.4 |
Assign Homework 1: Single Cycle Performance Assign Homework 2: Intel Machine Language |
| 4 | Mon. 23 Sep. | Multi-cycle CPU Microcode Quantum Computing, Part 1 |
Harris and Harris Section 7.4 Microcode |
Due Homework 1: Single Cycle Performance Assign Homework 3: Multicycle Microcode |
| 5 | Mon. 30 Sep. | Branch Prediction Dynamic Branch Prediciton Quantum Computing, Part 2 |
Agner Fog's microarchitecture guide (Read Section 3) H&P Section C.2 |
Due Homework 2: Intel Machine Language Assign Homework 4: Branch Prediction Assign Practice Test 1: |
| 6 | Mon. 7 Oct. | Two-Level adapative branch prediction Quantum Computing, Part 3 |
Agner Fog Optimization manual pages 9-11, 71-86, and 149-158 H&P Section 3.2 |
Due Homework 4: Branch Prediction Assign Homework 5: Two Level Adaptive Predictor Assign Homework 6: Observe Branch Prediction |
| 7 | Mon. 14 Oct. | Superscalar / Superpipeline | Harris and Harris Section 7.8 | Midterm Due Practice Test 1: |
| Wed. 16 Oct. | Due Homework 3: Multicycle Microcode | |||
| 8 | Mon. 21 Oct. | Fall Break | Assign Presentaton | |
| Wed. 23 Oct. | Due Homework 5: Two Level Adaptive Predictor Due Homework 6: Observe Branch Prediction |
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| 9 | Mon. 28 Oct. | Tomasulo's Algorithm | H&P Sections 3.4-3.6 | Assign Homework 7: Intel Differences |
| 10 | Mon. 4 Nov. | Cache Coherence | H&P Sections 5.1 - 5.4 | Due Presentation Proposal Due Homework 7: Intel Differences |
| 11 | Mon. 11 Nov. | Synchronization Cache Consistencey Wharehouse-scale computing |
H&P Sections 5.5 - 5.12 H&P Chaper 6 |
Assign Practice Final : |
| 12 | Mon. 18 Nov. | Vector/ SIMD/ GPU | H&P Chaper 4 | Assign Homework 8: Vector Processing (AVX) |
| 13 | Mon. 25 Nov. | Domain Specific Architectures | H&P Chaper 7 | Due Homework 8: Vector Processing (AVX) |
| 14 | Mon. 2 Dec. | Presentations | Due Presentaton Due Practice Final : |
|
| 15 | Mon. 9 Dec. | Final Exam |
| Due | Name | Details |
|---|---|---|
| Mon. 9 Sep. | First Day Survey | |
| Mon. 23 Sep. | Homework 1: Single Cycle Performance | |
| Mon. 30 Sep. | Homework 2: Intel Machine Language | |
| Mon. 7 Oct. | Homework 4: Branch Prediction | (only 1, 2, 4, and 5 due for credit.) |
| Mon. 14 Oct. | Practice Test 1: | (not due for credit) |
| Wed. 16 Oct. | Homework 3: Multicycle Microcode | |
| Wed. 23 Oct. | Homework 6: Observe Branch Prediction | |
| Wed. 23 Oct. | Homework 5: Two Level Adaptive Predictor | |
| Mon. 4 Nov. | Homework 7: Intel Differences | |
| Mon. 4 Nov. | Presentation Proposal | |
| Mon. 25 Nov. | Homework 8: Vector Processing (AVX) | |
| Mon. 2 Dec. | Presentaton | |
| Mon. 2 Dec. | Practice Final : | (not due for credit) |
| Date | Name | Details |
|---|
Updated Saturday, 23 November 2019, 12:58 PM