TLB

• Basic problem:
  • We just turned every memory access into two memory accesses.
  • Also, page tables are too big.
• How did we handle the latency of memory accesses in CIS 351?
  • A cache.
• Can we just rely on our existing cache mechanism to handle this?
  • Maybe; but, probably not.
    1. The cache is probably too small
    2. We would overwhelm the bus to/from the cache.
• But, we can build a separate cache just for the page table called the TLB
  • Translation Lookaside Buffer
  • Book proposed the more accurate term “Address-translation cache”
• Who is in charge of handling a TLB miss?
  • Two choices (a) hardware, (b) os.
• What are the pros and cons of each:
  • Hardware can be faster, but
  • Then the precise structure of the page table must be defined by the hardware.

• Notice that after the OS handles a TLB miss, the instruction must be started again. (Different from a typical trap/function call)

• A typical TLB is 32 to 128 entries and is fully associative.
  • (Compare that to the typical 8-16KB L1 cache.)
• What happens after a context switch? What are the options?
  • Flush TLB on context switch
  • Add an Address Space identifier.