CIS 351 |
Project 1: Build an Adder |
Winter 2021 |
For this project, you will use JLS to implement a signed adder.
You should work in teams of two. This project is a lot of work. Working alone is foolish.
Begin by following this GitHub Classroom link to create the repository for this project. You may want to copy your unsigned adder from the lab into this new repo.
Implement a 16-bit signed adder using any algorithm you
wish, provided the circuit has a reasonable running time and size.
Faster adders will receive more points. (See Grading
section below.) Your adder must report overflow conditions when they
occur (with respect to signed inputs).
Notice that this circuit must have an input named CarryIn
.
You will use this input for future projects.
The starter code contains a file named SignedAdder_16bit.jls
. You must place your solution
in this file. Do not change the names of any of the inputs or outputs. (If you change the filename
or the names of any inputs/outputs, the automated tests will not work.))
CarryOut
is the carry out from the last full adder. It is also,
in effect, the overflow indicator for unsigned inputs. Overflow
is the overflow
indicator for signed inputs. Remember, CarryOut
and Overflow
will not
necessarily have the same value.
You may use SampleSigned16BitAdderTest.java
as a basis for your own tests. Warning! This
test file is incomplete. Don't assume that a circuit that passes this sample test will pass all of my tests.
JLS
and DLUnit
. Commit and push your code often. That way, if JLS does crash
you won't lose too much work. Also, please e-mail me with any bugs you
find or feature requests you have. If JLS crashes, please e-mail me the
JLSerror
file.
This assignment will be scored out of 100 points.
Category | Rubric | Maximum Score |
---|---|---|
Functionality | ||
Not attempted | 0 | |
Substantially complete, but passes no tests | 15 | |
Passes a few tests | 25 | |
Correctly adds positive integers only | 45 | |
Correctly adds positive and negative integers (but overflow does not work correctly) |
55 | |
Passes all tests | 65 | |
Date 100% correct | ||
Two days early | 12 | |
One day early | 11 | |
On time | 10 | |
One day late | 8 | |
(-2 per day) | ... | |
Five or more days late | 0 | |
Date output correct |
||
On time | 10 | |
One day late | 8 | |
(-2 per day) | ... | |
Five or more days late | 0 | |
Speed | ||
≤ 75 | 9 | |
≤ 125 | 8 | |
≤ 175 | 7 | |
≤ 225 | 6 | |
≤ 275 | 5 | |
≤ 300 | 3 | |
> 300 | 0 | |
Presentation | ||
Size and Speed* | 5 |
*For 5 points, correctly specify the exact number of gates used by your adder (the total number of gates, including all sub-circuits) and the time required by your adder (i.e., the sum of all the gate delays along the critical path).
Penalties
To submit your project:
jls
files that includes the names of all team members.
[Grade Me]
in the commit message.Updated Monday, 28 December 2020, 6:03 PM