JLS is a powerful digital logic simulation tool created primarily for educational use. It includes a graphical editor that allows users to create and modify logic circuits, and a simulator that will show the operation of the circuit. It also has many features that are useful for classroom instruction and for the grading of student-designed circuits.
Logic circuits can contain the standard gate types: AND, OR, NOT, NAND, NOR, XOR, tri-state buffer and logically neutral time delay element; composite elements: decoder, multiplexor, and adder; memory elements: registers, SRAM, and ROM; a clock and various mechanisms for connecting gates and elements via wires and wiring elements. State machines can be created by using JLS's state machine editor. Combinational circuitry specified by a truth table can be generated by using JLS's truth table editor.
Circuits can include copies of other circuits (subcircuits), nested to an arbitrary depth. Circuits can be printed or exported as image (JPEG) files.