A JLS circuit consists of logic elements and connections between them (wires). A circuit may also contain (i.e., import) sub-circuits, nested to an arbitrary level. Text can be used to annotate a circuit.
JLS supports logic elements in several general categories: gates, components, memories and other. Gates are the common logic gates: AND, OR, NOT, NAND, NOR, and XOR, and also include a tri-state buffer and a logically neutral gate that simply delays its input signal by a given amount of time. Components are a multiplexor, decoder and adder. Memories are SRAM and ROM, and registers with various triggerings (level, edge). Other elements are a clock, elements that will pause and stop the simulator, and and element that will display its input value when the simulator pauses or stops.
Wiring is the connections between gates, and also includes mechanisms for bundling and unbundling multiple wire connections, expanding a single wire value into mutiple wires (useful for sign extension), generating constant values, and a mechanism for connecting wires without drawing lines across entire circuits.
JLS has a state machine editor that creates an element that implements a Moore-style statemachine directly from a user-drawn state diagram.
JLS also has a truth table editor that creates an element that implements a logic circuit directly from a user-drawn truth table.
Finally the user can create a signal generator element that outputs one or more arbitrary signals. This is very useful for testing new circuits.