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| Week | Date | Topics | Reading | Milestones | |
|---|---|---|---|---|---|
| 1 | Mon. 31 Aug. | Course Overview Introduction Truth Tables Circuit Overview How to build logic gates Use of Binary Hexadecimal and Base Conversions |
Video 0: Overview (In-Person) Video 0: Overview (Hybrid) Sections 1.1 - 1.5 Video 1 (CL1, CL3a) Video 2 (HW1) Video 3 (NR1c,d) Video 4 (NR1) Video 5 (NR3, NR4) Flippy bit A hexadecimal game Tom Lehrer's "New Math" |
Assign Homework 1a: First Day Survey Assign In-Class 1: Conversions Assign In-Class 2: Truth Tables and PLAs Assign Homework 1b: Relays Assign Homework 2a: Introduction to Digital Logic (Part 1) |
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| Wed. 2 Sep. | Truth tables / "Big Hammer" Failure of Big Hammer to Scale Combinatorial Circuits Other Gates Boolean Expressions |
Video 6 Section 2.4 Video 7 Sections 2.1, 2.4, and 2.5 (CL3b) Video 8 Sections 1.5.5 and 1.5.6 Video 9 Section 2.2 (CL3c,d) |
Due Homework 1a: First Day Survey Assign In-Class 3: Combinatorial Circuits Assign Homework 3a: JLS Setup |
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| Fri. 4 Sep. | Functional Completeness Busses / Bitwise logic operations |
Video 10 Section 2.9 |
Assign In-Class 4: Functional Completeness Assign In-Class 5: Busses and Bitwise Operations Due Homework 1b: Relays Assign Homework 2b: Introduction to Digital Logic (part 2) |
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| 2 | Mon. 7 Sep. | No Class | |||
| Wed. 9 Sep. | Adders Propagation Delay Time of Circuits Circuit Size |
Video 11 Section 5.2 Video 12 Section 1.6 (CL4) Video 13 Section 2.9 Video 14 |
Assign In-Class 6: Adder Assign In-Class 7: Propagation Delay Due Homework 2a: Introduction to Digital Logic (Part 1) Assign Homework 3a: JLS Setup Assign Project 1: Build an Adder |
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| Fri. 11 Sep. | Carry Lookahead Adder Quiz 1 |
Video 15a, Video 15b, Section 5.2 (ADD3cl) NR3, NR4, CL2, CL3 |
Due Homework 2b: Introduction to Digital Logic (part 2) Assign In-Class 8: AdvancedAdders Due Practice Quiz 1: |
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| 3 | Mon. 14 Sep. | Carry Lookahead Adder Carry Select Adder "Hybrid" adders / size/time tradeoff Diminishing returns |
Video 15a, Video 15b, Section 5.2 (ADD3cl) Video 16 (ADD3cs) |
Due Homework 3a: JLS Setup | |
| Wed. 16 Sep. | Signed Integers / Two's Complement Signed Addition |
Video 18 Section 1.4.6 (NR2) Video 19 (ADD4) |
Assign In-Class 9: Two's Complement Due Practice Quiz 2: |
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| Fri. 18 Sep. | Mulitplexors 2-to-1 mux is functionally complete Quiz 2 |
Video 22 (CL5) CL4, CL5, [NR3, NR4, CL2, CL3] |
Assign Homework 4a: Design Combinatorial Circuits Assign Homework 4b: Design Combinatorial Circuits (part 2) Assign In-Class 10: Circuit with Choices |
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| 4 | Mon. 21 Sep. | ALUs Complex Combinatorial Circuits Latches |
Video 22 (CL5) Video 23 Sections 3.1, 3.2, 3.3 (SL1) |
Assign Project 2: Build a Subtractor and SLT | |
| Wed. 23 Sep. | Clocks and Clocked Latches | Video 24 (SL2) Clocked D Latch |
Assign In-Class 11: SR-Latch Due Project 1: Build an Adder Due Practice Quiz 3: |
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| Fri. 25 Sep. | Quiz 3: | NR2, ADD4 [CL4] | Due Homework 4a: Design Combinatorial Circuits Due Homework 4b: Design Combinatorial Circuits (part 2) Assign Project 3: Build an ALU |
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| 5 | Mon. 28 Sep. | Exam 1 | |||
| Wed. 30 Sep. | Flip-Flops Sequential Circuits |
Video 25 Section 3.2.3 (SL2) Video 26 Sections 3.4, 3.5, and 3.6 (SL4, SL6) |
Assign In-Class 12: Flip Flop Timing Assign Homework 6a: Sequential Circuits (Part 1) Due Practice Quiz 4: Due Homework 4a: Design Combinatorial Circuits Due Homework 4b: Design Combinatorial Circuits (part 2) |
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| Fri. 2 Oct. | Flip-Flops Sequential Circuits Quiz 4: |
Video 25 Section 3.2.3 (SL2) Video 26 Sections 3.4, 3.5, and 3.6 (SL4, SL6) CL6 [NR2, ADD4] |
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| 6 | Mon. 5 Oct. | Finite state Machines Intro to CPU Design, Words, and Registers |
Video 27 Video 28 Sections 7.1 and 7.3.1 |
Assign Homework 7a: Sequential Circuits (Part 2) | |
| Wed. 7 Oct. | Machine languge and MIPS R-type Fetch/Execute cycle |
Video 29 Section 6.3 Video 30 Sections 7.1.3 and 7.3.1 |
Assign Homework 8a: Assembly Introduction Assign Homework 10a: Microarchitecture Due Project 2: Build a Subtractor and SLT Due Practice Quiz 5: |
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| Fri. 9 Oct. | Generating and Loading Machine Code Quiz 5: |
Video 31 SL2 [CL6] |
Due Homework 6a: Sequential Circuits (Part 1) | ||
| 7 | Mon. 12 Oct. | Assembly Basics Intro to MIPS Assembly |
Video33 Video 34 Sections 6.1, 6.2, 6.3, and 6.4.1 |
Assign In-Class 13: Assembly Intro | |
| Wed. 14 Oct. | I-Type instructions Design principles |
Video 32 Sections 6.5 and 6.7.1 Video 36 Sections 6.3.2, 7.3.2 and 7.3.3 |
Assign Homework 10b: Writing Assembly Due Practice Quiz 6: Due Homework 7a: Sequential Circuits (Part 2) |
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| Fri. 16 Oct. | Jump Branch Quiz 6: |
Video 37 Sections 6.3.3, 6.4.2, and 7.3 SL4 [SL2] |
Due Project 3: Build an ALU | ||
| 8 | Mon. 19 Oct. | Branch Writing assembly with branches |
Video 38 Sections 6.4.2, 6.4.3, and 6.4.4 |
Due Homework 8a: Assembly Introduction | |
| Wed. 21 Oct. | Design principles Load and Store |
Sections 6.3.2, 7.3.2 and 7.3.3 Section 6.4.5 |
Assign In-Class 14: Branches | ||
| Fri. 23 Oct. | slack / catch up Quiz 7: |
SL6, AL1 [SL4] | |||
| 9 | Mon. 26 Oct. | Fall Break | |||
| Wed. 28 Oct. | using .data in Assembly Load Store implementation Writing assembly with loops and memory |
Section 6.4.5 |
Assign Project 4: Build Single Cycle CPU Assign In-Class 15: Loops |
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| Fri. 30 Oct. | Quiz 8: Control Wires |
AL2, AL3 AL5 [SL6, AL1] Single Cycle Control Wires |
Assign In-Class 16: Control Wires | ||
| 10 | Mon. 2 Nov. | Exam 2 | |||
| Wed. 4 Nov. | Function calls Clobbered Registers Using "s" registers Heap and Stack |
Video 39 Section 6.4.6 Video 40 Video 41 Section 6.4.6 |
Due Homework 10a: Microarchitecture Assign Homework 11a: Stack and Functions |
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| Fri. 6 Nov. | Quiz 9: | AL4, SS3, [xAL2, AL3, AL5] | Due Homework 10b: Writing Assembly | ||
| 11 | Mon. 9 Nov. | Single Cycle Performance CISC vs. RISC |
Sections 7.2 and 7.3.4 | Assign Homework 9: Cache | |
| Wed. 11 Nov. | RAM SRAM Implementation DRAM Implementation SRAM vs. DRAM Memory layout |
Section 8.1 SRAM DRAM More DRAM SRAM vs. DRAM Section 8.3 |
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| Fri. 13 Nov. | Memory Heirarchy Motivation for caches Direct Mapped Cache Cache Block Size Quiz 10: |
Video 45 Section 8.1 Memory Heirarchy Video 46 Section 8.3 Video 47 SS4, SS5, [AL4, SS3] |
Due Homework 11a: Stack and Functions | ||
| 12 | Mon. 16 Nov. | Set Associative caches Cache replacement policy LRU and Pseudo-LRU |
Video 49 Section 8.3 Video 50 Video 51 |
Assign Homework 9: Cache Due Project 4: Build Single Cycle CPU |
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| Wed. 18 Nov. | LRU and Pseudo-LRU Split/Unified cache Write Through / Write Back cache |
Video 51 |
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| Fri. 20 Nov. | Pipelining Data Hazards Quiz 11: |
Intro to Pipelining Stages of MIPS pipeline Step through pipelined program Another Intro to Pipelining SS4, SS5, [AL4, SS3] |
Due Homework 11a: Stack and Functions | ||
| 13 | Mon. 23 Nov. | More Single Cycle Performance Superscalar |
Sections 7.2 and 7.3.4 | ||
| Wed. 25 Nov. | No Class | ||||
| Fri. 27 Nov. | No Class | ||||
| 14 | Mon. 30 Nov. | Exam 3 | Due Homework 9: Cache | ||
| Wed. 2 Dec. | Assign Homework 10: Pipeline Implementation Assign Homework 11: Pipeline Performance |
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| Fri. 4 Dec. | Quiz 12: | M2, M3, M4, [SS5] | |||
| 15 | Mon. 7 Dec. | ||||
| Wed. 9 Dec. | Interrupts Karnaugh Maps |
K-Map Introduction 4-variable K-map |
Due Homework 10: Pipeline Implementation Due Homework 11: Pipeline Performance |
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| Fri. 11 Dec. | Quiz 13: | P1, P2 [M2, M3, M4] | |||
| 16 | Mon. 14 Dec. | Final Exam: 4:00 p.m. |
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Updated Thursday, 22 October 2026, 1:16 PM