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| Week | Date | Topics | Reading | Milestones | |
|---|---|---|---|---|---|
| 1 | Mon. 25 Aug. | Course Overview Introduction Truth Tables Circuit Overview How to build logic gates Use of Binary Hexadecimal and Base Conversions |
General Policies and Proceedures Proficiency Grading Sections 1.1 - 1.5 Video 1 (CL1, CL3a) Video 2 (HW1) Video 3 (NR1c,d) Video 4 (NR1) Video 5 (NR3, NR4) Flippy bit A hexadecimal game Tom Lehrer's "New Math" |
Assign First Day Survey Assign In-Class 1: Conversions Assign In-Class 2: Truth Tables and PLAs Assign Homework 1: Relays Assign Homework 2: Introduction to Digital Logic Assign More Conversion Practice |
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| Wed. 27 Aug. | Truth tables / "Big Hammer" Failure of Big Hammer to Scale Combinatorial Circuits Other Gates Boolean Expressions |
Video 6 Section 2.4 Video 7 Sections 2.1, 2.4, and 2.5 (CL3b) Video 8 Sections 1.5.5 and 1.5.6 Video 9 Section 2.2 (CL3c,d) |
Due First Day Survey Assign In-Class 3: Combinatorial Circuits Assign Homework 3: JLS Setup |
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| Fri. 29 Aug. | Functional Completeness Busses / Bitwise logic operations |
Video 10 Section 2.9 |
Assign In-Class 4: Functional Completeness Assign In-Class 5: Busses and Bitwise Operations Due Homework 1: Relays |
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| 2 | Mon. 1 Sep. | No Class | |||
| Wed. 3 Sep. | Adders Propagation Delay Time of Circuits Circuit Size |
Video 11 Section 5.2 Video 12 Section 1.6 (CL4) Video 13 Section 2.9 Video 14 |
Assign In-Class 6: Adder Assign In-Class 7: Propagation Delay Due Homework 2: Introduction to Digital Logic Assign Project 1: Build an Adder |
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| Fri. 5 Sep. | Quiz 1: | NR3, NR4, CL2, CL3 | |||
| 3 | Mon. 8 Sep. | Carry Lookahead Adder | Video 15a, Video 15b, Section 5.2 (ADD3cl) |
Due Homework 3: JLS Setup | |
| Wed. 10 Sep. | Carry Lookahead Adder Carry Select Adder "Hybrid" adders / size/time tradeoff Diminishing returns Quiz 2: |
Video 15a, Video 15b, Section 5.2 (ADD3cl) Video 16 (ADD3cs) CL4, [NR3, NR4, CL2, CL3] |
Assign In-Class 9: AdvancedAdders | ||
| Fri. 12 Sep. | Signed Integers / Two's Complement Signed Addition |
Video 18 Section 1.4.6 (NR2) Video 19 (ADD4) |
Assign In-Class 8: Two's Complement | ||
| 4 | Mon. 15 Sep. | Mulitplexors 2-to-1 mux is functionally complete |
Video 22 (CL5) |
Assign Project 2: Build a Subtractor and SLT | |
| Wed. 17 Sep. | ALUs Complex Combinatorial Circuits Latches Quiz 3: |
Video 22 (CL5) Video 23 Sections 3.1, 3.2, 3.3 (SL1) NR2, ADD4 [CL4] |
Assign In-Class 10: Circuit with Choices Due Project 1: Build an Adder |
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| Fri. 19 Sep. | Assign In-Class 11: SR-Latch Assign Project 3: Build an ALU |
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| 5 | Mon. 22 Sep. | Clocks and Clocked Latches | Video 24 (SL2) Clocked D Latch |
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| Wed. 24 Sep. | Flip-Flops Sequential Circuits Quiz 4: |
Video 25 Section 3.2.3 (SL2) Video 26 Sections 3.4, 3.5, and 3.6 (SL4, SL6) CL5 [NR2, ADD4] |
Assign In-Class 12: Flip Flop Timing Assign Homework 4: Sequential Circuits Due Project 2: Build a Subtractor and SLT |
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| Fri. 26 Sep. | Flip-Flops Sequential Circuits |
Video 25 Section 3.2.3 (SL2) Video 26 Sections 3.4, 3.5, and 3.6 (SL4, SL6) |
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| 6 | Mon. 29 Sep. | Finite state Machines Intro to CPU Design, Words, and Registers |
Video 27 Video 28 Sections 7.1 and 7.3.1 |
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| Wed. 1 Oct. | Machine languge and MIPS R-type Fetch/Execute cycle Quiz 5: |
Video 29 Section 6.3 Video 30 Sections 7.1.3 and 7.3.1 CL5 [NR2, ADD4] |
Due Project 3: Build an ALU Assign Homework 5: Assembly Introduction / Microarchitecture |
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| Fri. 3 Oct. | Generating and Loading Machine Code | Video 31 | |||
| 7 | Mon. 6 Oct. | Assembly Basics Intro to MIPS Assembly |
Video33 Video 34 Sections 6.1, 6.2, 6.3, and 6.4.1 |
Assign In-Class 13: Assembly Intro Due Homework 4: Sequential Circuits |
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| Wed. 8 Oct. | I-Type instructions Design principles Quiz 6: |
Video 32 Sections 6.5 and 6.7.1 Video 36 Sections 6.3.2, 7.3.2 and 7.3.3 SL2 [CL5] |
Assign Homework 6: Writing Assembly | ||
| Fri. 10 Oct. | |||||
| 8 | Mon. 13 Oct. | Jump Branch |
Video 37 Sections 6.3.3, 6.4.2, and 7.3 Video 38 Sections 6.4.2, 6.4.3, and 6.4.4 |
Due Homework 5: Assembly Introduction / Microarchitecture | |
| Wed. 15 Oct. | Branch Writing assembly with branches Quiz 7: |
Video 38 Sections 6.4.2, 6.4.3, and 6.4.4 SL4SL6 [CL5] |
Assign In-Class 14: Branches | ||
| Fri. 17 Oct. | |||||
| 9 | Mon. 20 Oct. | No Class Fall Break | |||
| Wed. 22 Oct. | Design principles Load and Store |
Sections 6.3.2, 7.3.2 and 7.3.3 Section 6.4.5 |
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| Fri. 24 Oct. | using .data in Assembly Load Store implementation Writing assembly with loops and memory Quiz 8: |
Section 6.4.5 AL2 [SL4, SL6] |
Assign In-Class 15: Loops |
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| 10 | Mon. 27 Oct. | Control Wires | Single Cycle Control Wires | Assign In-Class 16: Control Wires | |
| Wed. 29 Oct. | Function calls Clobbered Registers Using "s" registers Heap and Stack Quiz 9: |
Video 39 Section 6.4.6 Video 40 Video 41 Section 6.4.6 AL3, AL4, AL5 [ AL2] |
Due Homework 6: Writing Assembly Assign Homework 7: Stack and Functions |
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| Fri. 31 Oct. | |||||
| 11 | Mon. 3 Nov. | Single Cycle Performance CISC vs. RISC |
Sections 7.2 and 7.3.4 | Due Lab 7: Loops and Memory Assign Homework 8: Cache |
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| Wed. 5 Nov. | RAM SRAM Implementation DRAM Implementation SRAM vs. DRAM Memory layout Quiz 10: |
Section 8.1 Section 8.3 SS3, SS4, [AL3, AL4, AL5] |
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| Fri. 7 Nov. | Memory Heirarchy Motivation for caches Direct Mapped Cache Cache Block Size |
Video 45 Section 8.1 Memory Heirarchy Video 46 Section 8.3 Video 47 |
Due Homework 7: Stack and Functions | ||
| 12 | Mon. 10 Nov. | Set Associative caches Cache replacement policy LRU and Pseudo-LRU |
Video 49 Section 8.3 Video 50 Video 51 |
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| Wed. 12 Nov. | LRU and Pseudo-LRU Split/Unified cache Write Through / Write Back cache Quiz 11: |
Video 51 SS5, [SS3, SS4] |
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| Fri. 14 Nov. | |||||
| 13 | Mon. 17 Nov. | Pipelining Data Hazards |
Intro to Pipelining Step through pipelined program |
Due Homework 8: Cache | |
| Wed. 19 Nov. | Pipelining Data Hazards Control Hazards Pipeline speedup / Limitations Quiz 12: |
Intro to Pipelining Step through pipelined program M2, M3, M4, [SS5] |
Assign Homework 8: Pipeline Implementation Assign Homework 9: Pipeline Performance |
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| Fri. 21 Nov. | |||||
| 14 | Mon. 24 Nov. | More Single Cycle Performance Superscalar |
Sections 7.2 and 7.3.4 | ||
| Wed. 26 Nov. | No Class Thanksgiving | ||||
| Fri. 28 Nov. | No Class Thanksgiving | ||||
| 15 | Mon. 1 Dec. | TBD | |||
| Wed. 3 Dec. | Interrupts Karnaugh Maps Quiz 13: |
K-Map Introduction 4-variable K-map P1, P2 [M2, M3, M4] |
Due Homework 8: Pipeline Implementation Due Homework 9: Pipeline Performance |
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| Fri. 5 Dec. | |||||
| 16 | Mon. 8 Dec. | Final Exam: 8:00 a.m. |
| Due | Name | Details |
|---|---|---|
| Wed. 27 Aug. | First Day Survey | |
| Fri. 29 Aug. | Homework 1: Relays | |
| Wed. 3 Sep. | Homework 2: Introduction to Digital Logic | |
| Mon. 8 Sep. | Homework 3: JLS Setup | |
| Wed. 17 Sep. | Project 1: Build an Adder | |
| Wed. 24 Sep. | Project 2: Build a Subtractor and SLT | |
| Wed. 1 Oct. | Project 3: Build an ALU | |
| Mon. 6 Oct. | Homework 4: Sequential Circuits | |
| Mon. 13 Oct. | Homework 5: Assembly Introduction / Microarchitecture | |
| Wed. 29 Oct. | Homework 6: Writing Assembly | |
| Fri. 7 Nov. | Homework 7: Stack and Functions | |
| Mon. 17 Nov. | Homework 8: Cache | |
| Wed. 3 Dec. | Homework 9: Pipeline Performance | Not due for credit |
| Wed. 3 Dec. | Homework 8: Pipeline Implementation |
| Date | Name | Details |
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Updated Wednesday, 6 August 2025, 12:40 PM