CIS 351

Project 1: Build a Signed Adder

Fall 2018

Due: Monday, 17 September 2018

For this project, you will use JLS to implement a signed adder.

Pre-requisites

The "Intro to JLS" lab provides an introduction to using JLS that you may find useful. This lab also explains how to obtain, set up, and use JLS, as well as use the DLUnit testing software. It is not due for credit.

This video demonstrates several helpful JLS shortcuts. Remember, JLS was designed specifically with these projects in mind. If you find a task highly repetitive/tedious, you are probably overlooking a shortcut.

Task

Implement a 16-bit signed adder using any algorithm you wish, provided the circuit has a reasonable running time and size. Faster adders will receive more points. (See Grading section below.) Your adder must report overflow conditions when they occur (with respect to signed inputs). Notice that this circuit must have an input named CarryIn. You will use this input for future projects.

Your inputs must be named InputA, InputB, and CarryIn. If not, your circuit won't work with my tests.

Your outputs must be named Output, CarryOut, and Overflow. CarryOut is the carry out from the last full adder. It is also, in effect, the overflow indicator for unsigned inputs. Overflow is the overflow indicator for signed inputs. Remember, CarryOut and Overflow will not necessarily have the same value.

You may use SampleSigned16BitAdderTest.java as a basis for your own tests. Warning! This test file is incomplete. Don't assume that a circuit that passes this sample test will pass all of my tests.

Rules

  1. You are strongly encouraged to work in groups of two. You may work alone only with permission of the instructor.
  2. The simulator comes with a built-in adder. You may not use the built-in adder.
  3. To build the required circuits, you will probably find it useful to design and build several subcircuits. These subcircuits may have any interface you choose; however, you are responsible for testing them.
  4. You must write all of your own chips. In other words, you may not share "internal" chips with your classmates, or download them off the Internet.
  5. Be sure to test your components thoroughly. Just because it passes the test included here doesn't mean it will pass my test.

Hints and shortcuts

Grading

This assignment will be scored out of 100 points.

Category Rubric Maximum Score
Functionality
Not attempted 0
Substantially complete, but passes no tests 15
Passes a few tests 25
Correctly adds positive integers only 45
Correctly adds positive and negative integers
(but overflow does not work correctly)
55
Passes all tests 65
Date 100% correct
Two days early 12
One day early 11
On time 10
One day late 8
(-2 per day) ...
Five or more days late 0
Date output correct
On time 10
One day late 8
(-2 per day) ...
Five or more days late 0
Speed
≤ 75 9
≤ 125 8
≤ 175 7
≤ 225 6
≤ 275 5
≤ 300 3
> 300 0
Presentation
Size and Speed* 5

*For 5 points, correctly specify the exact number of gates used by your adder (the total number of gates, including all sub-circuits) and the time required by your adder (i.e., the sum of all the gate delays along the critical path).

Penalties

Deliverables

To submit your project:

  1. Add a text box to your jls files that includes Your adder should also include a label indicating time and gate count. The time should be the maximum simulation needed for any addition. (I'm looking for an actual number, not a big-O expression.)
  2. Either

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